1. Field of the Invention
The present invention relates to semiconductor integrated circuits and methods of fabrication, and, in particular, to electrical isolation of devices in integrated circuits.
2. Description of the Related Art
The electrical isolation of active devices in silicon integrated circuit technology includes both general silicon oxide isolation in the "field" regions between devices and special application isolation structures. The most common isolation is the field region, which is typically implemented by partially or fully recessed thick oxide regions between active device regions (moats). Complete oxide isolation with no parasitic leakage paths is possible only in silicon-on-insulator (SOI) technologies. Special isolation structures, such as deep trenches, have been developed to separate the n and p well regions of complementary MOS (CMOS).
Almost all modern integrated circuits use LOCOS (local oxidation of silicon) for device isolation. A nitride/oxide stack is formed on the silicon substrate and is photolithographically patterned and etched to remove the nitride layer in the field regions. Oxidation then follows and the silicon is oxidized only locally in the field regions without nitride coverage. For PMOS the substrate is typically doped n type with phosphorus, and during oxidation the phosphorus segregates into the silicon so the oxide/silicon interface becomes heavily doped. In contrast, for NMOS the substrate is typically doped p type with boron, and during oxidation the boron segregates into the oxide and the oxide/silicon interface is depleted of dopants. The low interface doping for NMOS implies low threshold voltages for parasitic transistors and a need for "channel stop" doping at the interface to raise the parasitic threshold voltages. Consequently, before the resist is stripped off, additional boron impurities to form channel stops are implanted into the field regions. The thickness of the field oxide typically is between 0.7 and 1.0 .mu.m. Note that even for CMOS fabrication where adequate isolation structures are necessary between both n.sup.+ and p.sup.+ junctions, normally no additional lithographic step is needed for the channel-stop implant.
LOCOS advantageously allows introduction of the channel-stop impurities self-aligned to the field region, and it provides a smooth field oxide topography favorable for device fabrication. A major drawback of LOCOS is the so-called "bird's beak" transition between the field region and the moats which is caused by the lateral diffusion of oxidizing species beneath the nitride oxidation mask. The transition length varies depending on the oxidation condition, but is usually 0.3 .mu.m or more. This transition reduces the device packing density and, as the isolation area is scaled down for VLSI application, the problem becomes more serious.
Scaling down the field oxide thickness can reduce the bird's beak encroachment, but requires a heavier channel-stop implantation to maintain adequate isolation between the devices. The lateral diffusion of the channel-stop impurities during the field oxidation and subsequent high temperature processes can degrade junction capacitance, increase the junction leakage and reduce the "effective" electrical channel width associated with MOS current gain.
An option in scaling LOCOS is channel-stop implantation after the field oxidation; that is, implant channel-stop boron through the field oxide. This avoids the segregation of boron into the field oxide during the field oxidation, and retains more boron impurities near the oxide/silicon interface in silicon. As a result, thinner oxide can be used to achieve appropriate isolation; however, the threshold voltage for parasitic moat-to-moat transistors (with the field oxide acting as the transistor's gate oxide) is very sensitive to the oxide thickness. This is one of the problems associated with the through-field implant technique since the variation of field oxide thickness can be significant because for any local oxidation process the oxidation rate is a function of the width of the oxidizing space. If the space is less than 2 .mu.m wide, then the rate significantly reduces as the width is decreased. At 0.5 .mu.m wide space, the oxide thickness can be 30% less than bulk value. The reduction may be due to the overlap of the nitride stress from either edge of the pattern. The through-field implant for such thinner oxide regions will then penetrate the silicon substrate and have little impact on the doping level at the oxide/silicon interface and little channel stop effect.
Another problem associated with through-field implant is the increased junction capacitance and reduced junction breakdown voltage for n.sup.+ /p junctions. This is due to the increased substrate p dopant concentration under the junctions from the high energy, unmasked through-field implant. In principle a masked implant is possible to implant only the field regions in p type substrate. However, it's unpractical because patterning the field already is close to the lithographic limit, yet the implant mask requires patterning a geometry which is even smaller than the field to accommodate the alignment tolerance. With blanket implant without any mask (or a non-critical p well mask for CMOS), boron impurities are also implanted into the moat regions. The peak concentration may be on the order of 1.times.10.sup.17 /cm.sup.3 and the depth about the oxide thickness. As a result, the n.sup.+ /p junction capacitance as well as reversed junction leakage is increased. As the field oxide thickness is scaled down, the impurity profile is closer to the junction and the problem becomes more severe.
Modifications of the LOCOS process have been investigated. SILO, or Sealed-Interface Local Oxidation, uses an additional nitride layer, formed by plasma-enhanced nitridation, approximately 10 nm in thickness, to reduce the bird's beak; see J. Hui et al, 29 IEEE Tr.Elec.Dev. 554 (1982). Another approach uses a poly buffer layer between the nitride and the initial oxide; see R. Havemann et al, U.S. Pat. No. 4,541,167.
Several additional techniques have been investigated for reducing the amount of oxide encroachment, as replacements for standard LOCOS. Those that are sufficiently planar can be divided into three categories: (1) modified LOCOS that use improved nitridation masking, such as SWAMI, or MF3R, (2) recessed silicon regions (low to medium aspect "trenches") refilled by CVD oxide, such as BOX isolation, and (3) selective epitaxial growth (SEG). Non-planar techniques, such as direct moat isolation have been studied, but are not favored because of the patterning difficulties associated with subsequent levels such as interconnect.
In addition to improving subsequent patterning, such as avoiding filaments after anisotropic etching of gate interconnect, planarity is desirable because the recessed oxide structure is more effective in reducing the channel narrowing effect; see H. Iwai et al, 29 IEEE Tr.Elec.Dev. 625 (1982). Also, it is electrically superior in isolation. arising from an enhanced potential barrier at each bottom corner of the recessed oxide region; see S. Goodwin et al, 31 IEEE Tr.Elec.Dev. 861 (1984). Without sufficient recess, barriers do not exist because the diffused junctions overwhelm the two corners. As the isolation width is reduced, these enhanced barriers may dominate the isolation characteristics.
Unlike local oxidation process, BOX uses a deposited oxide. Thermal oxidation depletes the channel stop boron impurities near the interface which degrades the isolation. Using deposited oxide can retain more boron under the field and can achieve sharper corners with more potential barrier enhancement. However, the poorer oxide quality, even after densification or slight reoxidation, can produce a parasitic current path along the field oxide.
All of these modifications of and substitutes for LOCOS involve more complicated processing than standard LOCOS, and it is a problem to provide simple and efficient isolation in LOCOS as feature sizes scale down below 1 .mu.m.